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Apr 22 2025

Enabling complex HDL co-simulation scenarios using Renode's Direct Programming Interface support

Enabling complex HDL co-simulation scenarios using Renode's Direct Programming Interface support

When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation of elements of your design undergoing most heavy modifications with functional simulation using Antmicro's Renode framework for "best of both worlds" in terms of performance vs. accuracy. Read more

Feb 6 2025

Simplifying Renode model generation with SystemRDL-to-C# conversion

Simplifying Renode model generation with SystemRDL-to-C# conversion

SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable source of truth, SystemRDL provides a basis on which you can build other assets, such as SystemVerilog designs, test suites, software (drivers), and documentation. Read more

Jan 22 2025

Simulating ultra-low-power MSP430 MCUs in Renode

Simulating ultra-low-power MSP430 MCUs in Renode

The Texas Instruments MSP430 is a family of MCUs with its own custom ISA that enables ultra-low-power use cases. With a long history of supporting a breadth of products, including devices deployed in space, the most popular applications include performing highly reliable analog measurement functions, building automation and battery-management solutions as well as highly reliable IoT installations, and at Antmicro, we work with the MCU when developing power-constrained devices for our customers. Read more

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